This invention relates to the design of VLSI products and to arithmetic manipulation of numbers and particularly to multiplication of decimal system numbers.
Decimal multiplication using conventional binary coded decimal (BCD) notation is slower than the binary counterpart where the BCD coding is 8421. In this coding, a decimal number is represented by four bits, with values being assigned, from left to right, as 8421. That coding presents some invalid states for decimal numbers 10 through 15, preventing the use of conventional 3:2 compressor (adder) hardware used in parallel binary multiplication. Decimal multiplication is typically done one digit at a time, with partial products either being precomputed and stored in registers or evaluated as part of multiplication iteration, increasing the latency of the operation.
Recoding the multiplier is one technique for reducing the number of partial products that must be precomputed, but these are typically a signed digit notation requiring subtraction operations as well as addition operations when accumulating partial products. This again increases complexity of the operations.